In circuit arrangements designed using CMOS technologies, unwanted leakage currents play an ever greater role which is often no longer negligible. Especially for battery-operated appliances of all kinds, very small standby currents are often required which cannot be observed in more complex digital circuits on account of the leakage currents alone. A very effective measure for reducing the leakage current is to lower the operating voltage in standby mode. Since no further clock pulse is applied in standby mode, associated power losses are not relevant. The reduced voltage must merely be high enough for all the register contents to be maintained.
One simple method of voltage reduction involves connecting a diode between the supply connection of the circuit which is to be operated and the supply voltage connection of the circuit arrangement. For a positive supply voltage VDD, the voltage can be lowered by the diode threshold voltage VTH, for a negative supply voltage VSS, it can be raised by the diode threshold voltage VTH. For reasons of clarity, the text below considers only the case of a positive supply voltage VDD, since a person skilled in the art knows to apply the statements to circuit arrangements with negative supply voltages too. For normal mode with the full supply voltage, the diode is bridged by a switch, for example a PMOS transistor.
When the switch closes, two unwanted effects arise. Both the supply voltage connection and the supply connection at the lowered voltage have capacitances which have been charged to the respective voltage. When the diode is bridged by the switch, a voltage dip occurs in the supply voltage, since the capacitance at the lowered voltage needs to be charged to VDD by VTH. This voltage dip cannot be tolerated by certain circuit components. In addition, charging the capacitance at the lowered voltage results in a large current being briefly drawn in unwanted fashion which needs to be provided by the chip power supply.
One improvement is to connect the gate of the PMOS switching transistor to the supply voltage VDD via a capacitance. The gate connection is then connected to a current source which pulls down the gate voltage at a slower rate upon being turned on, which means that the PMOS switching transistor is not turned on abruptly. This makes it possible to eliminate the voltage dip at the supply voltage VDD. However, a drawback is that the current for charging the capacitance at the lowered voltage is not constant on account of the nonlinearity of the switching transistor, and is also subject to process and temperature fluctuations.